AI-driven design and optimization are revolutionizing RF and mixed-signal circuits for operation in extreme environments, including high radiation and wide temperature ranges. This talk explores the use of reinforcement learning (RL) and generative models to improve circuit robustness and adaptability. RL-based self-healing techniques leverage embedded electromagnetic sensors for real-time monitoring and dynamic fault recovery, while generative models accelerate design space exploration, enabling resilient and efficient circuit topologies. The presentation will highlight AI-enhanced designs such as adaptive power amplifiers, PMICs, and multispectral sensors that enhance performance and reliability in harsh environments.

Vanessa Chen earned her Ph.D. in electrical and computer engineering from Carnegie Mellon University in 2013. Before joining Carnegie Mellon University, she was affiliated with The Ohio State University. During her doctoral studies at Carnegie Mellon from 2010 to 2013, she conducted research on algorithm-assisted approaches for improving energy efficiency and ultra-high-speed ADCs with on-chip real-time calibration, and interned at IBM T. J. Watson Research Center in 2012. Prior to academia, she held positions as a circuit designer at Qualcomm in San Diego and Realtek, Hsinchu, Taiwan, focusing on self-healing RF/Mixed-signal circuits. Her research focuses on AI-enhanced circuits and systems, which include intelligent sensory interfaces, RF/mixed-signal hardware security, and ubiquitous sensing and computing systems. Dr. Chen has received the NSF CAREER Award in 2019. She has been involved in various technical program committees, including ISSCC, VLSI, CICC, A-SSCC, and DAC. She also has served as an Associate Editor for several IEEE journals, including TCAS-I, TBioCAS, and OJCAS. Additionally, she has contributed as a Guest Editor for TCAS-II and ACM JETC. She is currently an IEEE SSCS Distinguished Lecturer in 2025/2026.

As data converters find their way into virtually every microelectronic device, developers of application-specific systems-on-a-chip increasingly suffer from large development costs arising from limited specialized design expertise and the tedious process of migration to new technology nodes. In this talk, we introduce three pieces of analysis for the optimum design of key building blocks in the ADC: a) Distortion and bandwidth of a passive sample and hold (S/H) circuit, b) noise and offset of a regenerative comparator, and c) jitter analysis for a clock distribution path. By deploying these analysis tools, a systematic design framework for ADCs is demonstrated, along with the optimized design of a self-timed charge-redistribution SAR ADC.

Tetsuya Iizuka received the B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2002, 2004, and 2007, respectively. From 2007 to 2009, he was with THine Electronics Inc., Tokyo, as a High-Speed Serial Interface Circuit Engineer. He joined the University of Tokyo in 2009, where he is currently a Professor in the Department of Electrical Engineering and Information Systems, School of Engineering. From 2013 to 2015, he was a Visiting Scholar with the University of California at Los Angeles, Los Angeles, CA, USA. His current research interests include data conversion techniques, high-speed analog integrated circuits, digitally assisted analog circuits, and VLSI computer-aided design. He was a member of the IEEE International Solid-State Circuits Conference (ISSCC) Technical Program Committee from 2013 to 2017 and a member of the IEEE Custom Integrated Circuits Conference (CICC) Technical Program Committee from 2014 to 2019. From 2016 to 2018, he served as the Editor for IEICE Electronics Express (ELEX). Since 2025, he has served as a distinguished lecturer of the IEEE Solid-State Circuits Society (SSCS). He is also serving as a member of the IEEE Asian Solid-State Circuits Conference (A-SSCC) and the IEEE VLSI Symposium on Circuits Technical Program Committees. He was a recipient of the 21st Marubun Research Encouragement Commendation from Marubun Research Promotion Foundation in 2018, the 13th Wakashachi Encouragement Award First Prize in 2019, the 18th Funai Academic Prize from Funai Foundation for Information Technology in 2019, and the 42nd Yazaki Academic Achievement Award from Yazaki Memorial Foundation for Science and Technology in 2025. He was a co-recipient of the IEEE International Test Conference Ned Kornfield Best Paper Award in 2016.

The compute demands of AI and robotics continue to rise due to the rapidly growing volume of data to be processed; the increasingly complex algorithms for higher quality of results; and the demands for energy efficiency and real-time performance. In this talk, we will discuss the design of efficient hardware accelerators and the co-design of algorithms and hardware that reduce the energy consumption while delivering real-time and robust performance for applications including deep neural networks, data analytics with sparse tensor algebra, and autonomous navigation. We will also discuss our recent work that balances flexibility and efficiency for domain-specific accelerators and reduce the cost of analog-to-digital converters for processing-in-memory accelerators. Throughout the talk, we will highlight important design principles, methodologies, and tools that can facilitate an effective design process.

Vivienne Sze is a professor in MIT's Department of Electrical Engineering and Computer Science. Her group works on computing systems that enable energy-efficient machine learning, computer vision, and video compression/processing for a wide range of applications, including autonomous navigation, digital health, and the internet of things. She is widely recognized for her leading work in these areas and has received many awards, including faculty awards from Google, Facebook, and Qualcomm, the Symposium on VLSI Circuits Best Student Paper Award, the IEEE Custom Integrated Circuits Conference Outstanding Invited Paper Award, and the IEEE Micro Top Picks Award. As a member of the Joint Collaborative Team on Video Coding, she received the Primetime Engineering Emmy Award for the development of the High-Efficiency Video Coding video compression standard. She is a co-author of the book entitled "Efficient Processing of Deep Neural Networks". information about Prof. Sze's research, please visit: http://sze.mit.edu