Short Course 1

January 15. 2007 14:30-17:30
SANJO-Conference Hall 2F, Hongo, The Univeristy of Tokyo

3D Integration Technologies - An Overview

Lecturer: Dr. Rajen Chanchani

IEEE Distinguished Lecturer(DL) and Fellow, IEEE-CPMT Society

Course Scope and Objective
An overview of 3D integration technologies will be presented. The course will include the motivation, description of the key technologies and their status.

The main motivating factors are:
1. 3D integration enables miniaturization of microsystems.
2. A wider variety of technologies can be integrated with 3D integration.
3. Electrical performance of 3D technology will be better.

In this course, 3D integration technologies are divided into three categories – on-chip 3D integration, 3D integration of ICs and 3D Packaging. On-chip 3D integration is a ‘bottom-up’ approach in which active layers in an IC are built-up over an IC wafer. The second category is a ‘top-down’ approach, in which different ICs are first fabricated independently and then stacked in 3D. In the third category, the ICs are packaged in 3D. In this course, I will describe all these technologies. The issues associated with each category of technologies will also be presented. These issues are thermal dissipation, higher cost and lower yields. In spite of these issues, 3D technology looks very promising in solving the problems faced by 2D technologies.

Who Should Attend
Engineers and managers working in packaging, electronic and system-level design field already involved in 3D technologies or newcomers wanting fundamental understanding will greatly benefit from this course. In addition, the current suppliers of materials and equipment who seek to know more about the existing and future 3D Integration options will also benefit from this workshop.

Course Outline

1.	Introduction
2.	What is 3D Integration?
3.	Types of 3D Integration Technologies
4.	Motivation for 3D Integration
5.	Commercial Availability
6.	Description of 3D ICs
7.	Description of 3D Integration of ICs
8.	Description of 3D Packaging
9.	Cost Issues
10.	Thermal Management Issues
11.	Applications
12.	Conclusions

Biography

Rajen Chanchani is currently Principal Member of Technical Staff, Sandia National Laboratories, Albuquerque. He received his Ph.D. and M.S. in Materials Science & Engineering from the University of Florida in 1984 and B. Tech. from the Indian Institute of Technology, Kanpur, India, in 1973. Rajen has an extensive experience in 3D Integration technologies, micro-systems packaging, chip-scale-packaging, multi-chip modules, thin and thick-film, chip-on-board, flip-chip, MEMS packaging and surface mount technologies and modelling & simulation. Rajen is an IEEE Fellow, International Microelectronic and Packaging Society (IMAPS) Fellow. Rajen is also a recipient of William D. Ashman Award for his contribution to advance packaging technologies. Rajen has published over 70 papers and has two patents. He has received Best Paper Award in IMAPS Annual Conference paper in 1994, and in Micro System Technologies 2005 . At Sandia National Labs, Rajen has been managing packaging-related projects for the defence and non-defence applications since 1990. Prior to joining Sandia National Labs, Rajen worked at ATx Bell Laboratories in Allentown, PA.