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Lecture
Monitorology and Big Data in the Age of Data Analytics
Date: 22 July 2016
Time: 15:00 – 16:30
Location: Hiroshima City University
http://www.hiroshima-cu.ac.jp/page/content0005.html
</font>
Sponsored: Hiroshima City University
Co-sponsored:IEEE Hiroshima Section
Title: Monitorology and Big Data in the Age of Data Analytics
Speaker: Prof. Miroslaw Malek (Universita della Svizzera italiana)
Abstract:
We focus on the art of observing the world by humans and electronic devices such as sensors and meters that, in general, we call monitors. We then move to monitoring devices, define main monitoring objectives and pose five challenges for effective and efficient monitoring that still need a lot of research. In the age of computricity, where compute power like electricity is easily available and easy to use across the globe, and big data that is generated in enormous amounts and ever-increasing rates, the question, what to monitor and how, will become ever more relevant to save the world from flood of meaningless, dumb data, leading frequently to false conclusions and wrong decisions whose impact may range from a minor inconvenience to loss of lives and major disasters.
We argue, that in the age of Big Data, current complexity levels and necessity of dealing with time, in addition to classical synthesis and analysis methods, we need to turn to empirical data-driven approaches using data analytics to, for example, proactive fault management which require monitoring, online measurement, online analysis, diagnosis, failure prediction and decision making to support recovery and nonstop computing and communication. To illustrate such approaches two case studies are presented: In the first case study, we address the problem of proactive fault management by demonstrating how runtime monitoring, variable selection and model re-evaluation lead to effective failure prediction.
We also present the quality analysis of such prediction to determine whether it results in dependability gain. The second case study illustrates how by observation and measurement of CPU and memory features a malicious software (malware) can be detected on line. Finally, we conclude that models derived from monitoring and measurement will continue gaining on significance and impact and list the major challenges for data-driven research on dependability and security.
Gains in IEEE Hiroshima Section Symposium
Date: 22 May 2016
Time: 13:00-13:30
Location: Yamaguchi University (Tokiwa Campus)
Sponsored: IEEE Hiroshima Section
Speaker: Prof. Hotta (Yamaguchi University)
Tide of recent date in payment services
Date: 14 Apr. 2016
Time: 15:00-16:45
Location: Matsue Terrsa (Matsue City)
Sponsored: IEEE Hiroshima Section
Speaker: Mr. Keiji MINAMI (Sony Payment Services)
The Time-Triggered Architecture
Date: 8 Apr. 2016
Time: 14:00-15:30
Location: Hiroshima City University http://www.hiroshima-cu.ac.jp/page/content0005.html
Sponsored: Hiroshima City University
Supported: IEEE Hiroshima Section
Speaker: Em.Prof. Dr. Hermann Kopetz (Vienna University of Technology)
Abstract: The Time-Triggered Architecture (TTA) provides a computing infrastructure for the design and implementation of dependable distributed embedded systems that is widely deployed in industry, e.g., in the Boeing 787 aircraft or the NASA Orion Spacecraft. A large real-time application is decomposed into nearly autonomous clusters and
nodes, and a fault-tolerant global time base of known precision is generated at every node. In the TTA, this global time is used to precisely specify the interfaces among the nodes, to simplify the communication and agreement protocols, to perform prompt error detection, and to guarantee the timeliness of real-time applications. The TTA supports a two-phased design methodology, architecture design, and component design. During the architecture design phase, the interactions among the distributed components and the interfaces of the components are fully specified in the value domain and in the temporal domain. In the succeeding component implementation phase, the components are built, taking these interface specifications as constraints. This two-phased design methodology is a prerequisite for the composability of applications implemented in the TTA and for the reuse of prevalidated components within the TTA. This talk presents the architecture model of the TTA, explains the design rationale, discusses the time-triggered communication protocols TTP/C and TT-Ethernet, and illustrates how transparent fault tolerance can be implemented in the TTA.
Past lectures
2017 / 2016 / 2015 / 2014 / 2013 / 2012 / 2011