SSCS Japan Chapter / Kansai Chapter Lecutre Tuesday 10th December, 2019, 10:00 ? 12:00 Room 402, Takeda Building, the University of Tokyo 1) "Design of a Low-Power Low-Jitter Multi-Output Clock Generation System" Prof. Tsung-Hsien Lin, National Taiwan University Abstract: In typical SoC systems, various clock signals are required to support different circuit functions. These clock frequency ranges from kHz-range for timekeeping to several hundred MHz and above for high-performance computing operation. Traditionally, these clocks are generated with multiple phase-locked looks (PLLs) and possibly with multiple crystals. In this work, we propose a multi-output clock generation system that produces multiple clock signals using fractional output dividers (FODs) while only one crystal oscillator and one low-power PLL is employed. This system can support clock frequency ranges from 32.768 kHz to several hundred MHz. Bio: Tsung-Hsien Lin received his MS and Ph.D. degrees in electrical engineering from UCLA, in 1997 and 2001, respectively. In 2000, he joined Broadcom Corporation, Irvine, CA, where he was a Senior Staff Scientist, during which time he involved in wireless transceiver developments. In 2004, he joined the Department of Electrical Engineering, National Taiwan University, Taiwan, where he is now a Professor. His research interests are the design of wireless transceivers, clock and frequency generation systems, delta-sigma modulators, and transducer interface circuits. He is currently serving as the Director of Graduate Institute of Electronics Engineering (GIEE), NTU, starting Aug. 2019. Dr. Lin was the recipient of the Best Presentation Award for his paper presented at the 2007 VLSI-DAT Symposium, and the co-recipient of the Best Paper Award at the same Symposium in 2015. He served on the IEEE Asian Solid-State Circuit Conference (A-SSCC) Technical Program Committee (TPC) from 2005 to 2011 and was the TPC Vice-Chair for 2011 A-SSCC. He was a Guest Editor for IEEE Journal of Solid-State Circuits (JSSC) in 2012 and 2018, and was an Associate Editor for the same journal from 2013 to 2015. He served on the ISSCC International Technical Program Committee from 2010 to 2016, and was the Far-East Regional Committee Chair in 2016 ISSCC. He was the TPC Chair of 2017 A-SSCC and is the TPC Co-Chair of 2020 VLSI-DAT. 2) "Accelerating Data Analysis for DNA Sequencing" Prof. Chia-Hsiang Yang, National Taiwan University Abstract: DNA sequencing is the process of determining the precise order of nitrogenous bases within a DNA molecule. It is now an indispensable tool for determining the cause of genetic diseases and for developing associated treatments. Next-generation sequencing (NGS) is currently the fastest sequencing technique and can sequence the short fragments in a massively parallel fashion, achieving orders of magnitude higher throughput than the first-generation sequencing technique. However, as the throughput of NGS growth exponentially, the succeeding data processing and analysis are still excessively time consuming. In this talk, I will present an NGS data processor ASIC that realizes DNA mapping, including suffix array (SA) sorting and backward searching. An efficient hardware architecture is proposed to perform the extremely time-consuming SA sorting. With the optimized hardware parameters, memory usage and processing latency are significantly reduced. The chip achieves four orders of magnitude energy efficiency improvement over the GPU solution. Bio: Chia-Hsiang Yang (Mf10-SMf17) received his B.S. and M.S. degrees from the National Taiwan University, Taiwan, in 2002 and 2004, respectively, all in Electrical Engineering. He received his Ph.D. degree from the Department of Electrical Engineering of the University of California, Los Angeles in 2010. He then joined the faculty of the Electronics Engineering Department at the National Chiao Tung University, Taiwan. In 2015, he moved to the National Taiwan University, Taiwan, where he is currently a Full Professor. His research interests include energy-efficient integrated circuits and architectures for biomedical and communication signal processing. Dr. Yang was a winner of the DAC/ISSCC Student Design Contest in 2010. He received the 2010 -2011 Distinguished Ph.D. Dissertation in Circuits & Embedded Systems Award from the Department of Electrical Engineering, University of California, Los Angeles. In 2013, he was a co-recipient of the ISSCC Distinguished-Technical-Paper Award and Demonstration Session Certification of Recognition. He is also the advisor for several student awards, including the 2017 ISSCC Silkroad Award. He has served on the IEEE Asian Solid-State Circuit Conference (A-SSCC) Technical Program Committee and ISSCC Student Research Preview (SRP) Committee. He also served as a Guest Editor of the IEEE Journal of Solid-State Circuits (JSSC) and is also serving as an Associate Editor of the IEEE Signal Processing Letters (SPL).