IEEE EDS Japan Chapter 会員各位
IEEE EDS Kansai Chapter 会員各位
IEEE Electron Devices Society Japan Chapter
Chair 木村
紳一郎
Vice Chair 鳥海 明
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DL(Distinguished Lecturer)講演会のお知らせ
IEEE EDS Distinguished LecturerのStanford大学 西
義雄教授による下記のDL講演会を開催致します。皆様のご参加を頂きたくご案内申し上げます。
【日 時】平成23年11月11日(金)午後 4時 〜 5時
【会 場】東京工業大学すずかけ台キャンパスS2棟7階 会議室
(横浜市緑区長津田町4259、最寄り駅:東急田園都市線すずかけ台駅)
会場地図は下記サイトをご参照下さい。
http://www.titech.ac.jp/about/campus/s_map.html
【講演者】西 義雄教授(Professor of
Electrical Engineering, Material Science and Engineering, Director of Research,
Center for Integrated Systems, Standford University,
USA)
【タイトル】
" Challenges in Nanoelectronic
Devices and Integrations on Silicon Platform Today and Tomorrow"
【概要】
There is widely shared concern today that as we approach future technology nodes of CMOS beyond sub-20nm, diminishing return in device performance and density combined with serious increase in on-chip power consumption would force us to seek for possible alternatives beyond simple scaling of the minimum geometry. Applications of mechanical strain to MOSFET channel for improved transport characteristics, material alternatives for conductive channel of MOSFET such as germanium and/or III-V semiconductor, intensive study for partial replacement of on-chip interconnects with optical interconnect, new nonvolatile memory phenomena thereby feasibility of new memory devices such as resistive switching are only a part of such efforts in addition to global trend of going 3D devices and integration. Also mentioned should include a variety of “nano” materials such as carbon nano tube, graphene etc, which might capture unique positions in an integrated circuit technology a rsenal with further in-depth understanding and technologicalbreak-through for controlling their characteristics. This talk will discuss a perspective of a variety of nanoelectronic devices to be integrated on silicon platform, and where they would likely be heading toward.
【略歴】
He received a BS degree in materials
science and a PhD in electronics engineering from Waseda
University and the University of Tokyo, respectively. In 1962, he joined
Toshiba R&D working mainly on Si based CMOS devices and technology until
the mid 80’s, including developments of the world first 1MCMOS DRAM, 16 bit SOS
processor technology, MNOS nonvolatile memory. His early discovery of electron
spin resonance Center, PB,from silicon-silicon
dioxide has been recognized as the origin of the fast interface states. In 1986
he joined Hewlett-Packard as the director of the Silicon Process Lab, and led
CMOS R&D for HP-PARISC processors, followed by the founding director of HP
ULSI Research Laboratory.
In 1995 he joined Texas Instruments Inc, as Senior Vice President and Director
of R&D in which he established new R&D model and Kilby
Center for TI’s IC technology R&D. In 2002 he switched from industry to
academia as a faculty member of Stanford University, where he serves as a
professor in the Department of Electrical Eng ineering
(research) and also in the Department of Material Science and Engineering. He
also se rves as director of research of the Center
for Integrated Systems. His research interest covers nanoelectronic
devices and materials including a metal gate/high-k MOS, a device layer
transfer for 3D integration, nanowire devices, Group
IV light emitting devices, and resistance change nonvolatile memory materials
and devices.
Prof. Nishi is IEEE Fellow, and received
numerous awards, including 1995 Jack Morton Award, 2002 Robert Noyce Medal, 2006 PICMET Technology Mnagement
Leadership Award, 2008 SEMI North America Lifetime Achievements Award. He is
one of the founding members of VLSI Symposia. He has served as visiting
professor of Waseda University, Tsinghua
University, Peking University, International Advisory Committee member of
Solid-State Devices and Materials Conference, Executive Committee member of
IEEE VLSI Symposium,and also technical advisory board
of several companies. During the period of 1995?2002, he served as a board
member of the SRC and the International Sematech, the
NNI panel, the MARCO governing council, and other boards. Currently, he serves
as an affiliated member of the Science Council of Japan and a member of the
International Scientific Advisory Board of the Central European Inst itute of Technology (CEITEC). Lately he is elected as
professor for the Chair of Excellence, Nanoscience
Foundation, France.
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<現地連絡先>
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東京工業大学 フロンティア研究機構
岩 井 洋
〒226-8502 横浜市緑区長津田町4259
Mail-Box:J2-68
TEL:045-924-5471
FAX:045-924-5584
E-mail:iwai.h.aa@m.titech.ac.jp
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IEEE EDS Japan Chapter連絡先:Secretary 鳥居 和功
E-mail:kazuyoshi.torii@ieee.org
Home page:http://www.ieee-jp.org/section/tokyo/chapter/ED-15/
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