IEEE Circuits and Systems Society Japan Joint Chapter
(Tokyo/Hiroshima/Nagoya/Sapporo/Sendai/Shin-Etsu/Japan Council Joint Sections Chapter)
(Tokyo/HR/NG/SP/SE/SD Jt Sec Chap)
[Japan Council : Chapters一覧]
Shmuel Wimer先生 講演会
東京工業大学 大岡山キャンパス 本館H114講義室
- 題目： Post-Silicon Analysis of Shielded Interconnect Delays for Useful Skew Clock Design
- 講師： Prof. Shmuel Wimer (東工大特任教授, Bar-Ilan University名誉教授)
- 概要： Analyses and simulations have shown that interconnect shielding can replace a large fraction of the delay buffers
used to achieve timing goals through a useful skew clock design methodology.
Immunity from process, operation, and environmental variations in nanoscale CMOS technology clock designs are essential,
thus making predictable delays and useful skews highly important.
We examine interconnect shielding intra die within-die (WID) and inter die die-to-die (D2D) variations under a wide variety of (P,V,T) corners,
and show their applicability and ability to achieve clock design timing goals.
The analysis is based on post-silicon measurements of a novel shielded interconnect ring oscillator in a 16-nm test chip
supported by a rigorous provable estimation methodology.
- 略歴： Shmuel Wimer is a Professor Emeritus with the Engineering Faculty of Bar-Ilan University, Israel.
He received his B.Sc. and M.Sc. degrees in Mathematics from Tel-Aviv University, Israel, in 1978 and 1981, respectively,
and his D.Sc. degree in Electrical Engineering from the Technion-Israel Institute of Technology, Israel, in 1988.
From 1978 to 2009 he held R&D, engineering and managerial positions in industry.
From 1999 to 2009 he was with Intel, and prior to that with IBM, National Semiconductor, and the IAI-Israel Aerospace Industry.
Since 2009 he is with Bar-Ilan University.
His interests are in VLSI circuits and systems design optimization and combinatorial optimization.
連絡先： 東京工業大学 高橋篤司(firstname.lastname@example.org)
Nan Sun先生 講演会
東京工業大学 大岡山キャンパス 南4号館2階S422
- 題目： New Ingredients in the Pot - Rethink Analog IC Design -
- 講師： Prof. Nan Sun (Associate Professor at the University of Texas, Austin)
- 概要： I will present several unconventional data conversion architectures.
First, I will talk about how we can make use of noise, which is usually deemed as an undesirable thing,
to estimate the conversion residue and increase the SNR of a SAR ADC.
It is an interesting example of stochastic resonance, in which the presence of noise can lead to not SNR degradation but SNR enhancement.
Second, I will talk about how we can perform data conversion below the Nyquist rate by exploiting the sparsity of the input signal.
I will show two example compressive sensing ADCs and how the effective ADC conversion rate can be reduced by 4 times but without losing information.
Third, I will show how we can prevent the seemingly inevitable kT/C noise in a Nyquist-rate pipelined ADC by using a continuous-time SAR based 1st-stage.
This can substantially reduce the requirement on the ADC input capacitance, greatly reducing the ADC driver power and reference buffer power.
Mohammed Ismail先生 講演会
東京工業大学 大岡山キャンパス 南3号館2階第一会議室
- 題目： A Self-powered IoT SoC Platform for Wearable Health Care
- 講師： Prof. Mohammed Ismail (Professor and Chair of ECE at Wayne State University, Detroit / IEEE Fellow / Adjunct professor with KUSTAR, Abu Dhabi, UAE)
- 概要： This talk will focus on an IoT Systems-on-Chip (SoCs) as part of research work which targets applications in self-powered chip sets
for use in public health, ambient intelligence, safety and security and IoT.
One such application, which we will discuss in details, is a ground breaking self-powered IoT SoC platform for wearable health care.
More specifically we will present a novel fully integrated ECG signal processing system for the prediction of ventricular arrhythmia using
a unique set of ECG features extracted from two consecutive cardiac cycles.
Two databases of the heart signal recordings from the American Heart Association (AHA) and the MIT PhysioNet were used as training,
test and validation sets to evaluate the performance of the proposed system.
The system achieved an accuracy of 99%.
The ECG signal is sensed using a flexible, dry, Graphene-based technology and the system is powered up by harvesting human thermal energy.
The system architecture is implemented in Global foundries' 65 nm CMOS process, occupies 0.112 mm2 and consumes 2.78 micro Watt at an operating
frequency of 10 KHz and from a supply voltage of 1.2V.
To our knowledge, this is the first SoC implementation of an ECG-based processor that is capable of predicting ventricular arrhythmia hours
before the onset and with an accuracy of 99%.
連絡先： 東京工業大学 佐藤広生(email@example.com)
IEEE CASS JJCは、電子情報通信学会回路とシステム研究会を協賛しています．
IEEE CASS JJC Best Student Award (Technical Meeting of Circuits and Systems) を授与します．
|| 牧野 光則 Makino, Mitsunori
|| 高橋 篤司 Takahashi, Atsushi
||戸川 望 Togawa, Nozomu
||岸田 亮 Kishida, Ryo