IEEE SSCS Kansai Chapter Technical Seminar

IEEE SSCS Kansai Chapterでは,下記の日程で技術セミナーを開催致します.
今回はSymposia on VLSI Technology/Circuits 国内報告会として, 2021 Symposia on VLSI Technology/Circuits で講演された方をお招きします. 従来は Circuits のみを対象としていましたが, 今回は IEEE EDS Society と合同で Technology および Joint Session での講演者もお招きしており, 例年以上に多数の講演を聴講いただけます.

2021年7月30日(金)10:00より17:00 (予定)
IEEE Solid-State Circuits Society Kansai Chapter, IEEE Electron Devices Society Kansai Chapter
IEEE Solid-State Circuits Society Japan Chapter, IEEE Electron Devices Society Japan Chapter
10:00-10:05OpeningKazutoshi Kobayashi (Kyoto Institute of Technology)
10:05-10:20VLSI Symposia ReviewYusuke Oike (Sony), Katsura Miyashita (Toshiba)
10:20-10:25ISSCC 2022 Call for PapersJun Deguchi (Kioxia), Munehiko Nagatani (NTT)
Session 1 (Chair: Takashi Hashimoto (Panasonic))
10:25-10:40 A 6.78 MHz Wireless Power Transfer System for Simultaneous Charging of Multiple Receivers with Maximum Efficiency using Adaptive Magnetic Field Distributor ICHao Qiu (The University of Tokyo)
10:40-10:55 On-Silicon Photonic Integrated Circuit toward On-Chip Interconnection and Distributed ComputingNobuhiko Nishiyama (Tokyo Institute of Technology)
10:55-11:10A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter with 24-GHz Wireless Power and LO TransferMichihiro Ide (Tokyo Institute of Technology)
11:10-11:25A Fast-Beam-Switching 28-GHz Phased-Array Transceiver Supporting Cross-Polarization Leakage Self-CancellationJian Pang (Tokyo Institute of Technology)
11:25-11:40A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise EnhancementRuilin Zhang (Waseda University )
11:40-11:55Breakout session (QA session)
11:55-13:00Lunch break
Session 2 (Chair: Mutsunori Uenuma (NAIST))
13:00-13:15A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference SpurZule Xu (The University of Tokyo)
13:15-13:30Superconducting Quantum Computer: a Hint for Building ArchitecturesYutaka Tabuchi (The Univ. of Tokyo)
13:30-13:45Buried Nanomagnet Realizing High-Speed/Low-Variability Silicon Spin Qubits: Implementable in Error-Correctable Large-Scale Quantum ComputersShota Iizuka (AIST)
13:45-14:00A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera SystemsNorihito Kato (Renesas Electronics Corporation)
14:00-14:15Strategy toward HZO BEOL-FeRAM with Low-Voltage Operation (≤ 1.2 V), Low Process Temperature, and High Endurance by Thickness ScalingKasidit Toprasertpong (The Univ. of Tokyo)
14:15-14:30Critical Role of GIDL Current for Erase Operation in 3D Vertical FeFET and Compact Long-Term FeFET Retention ModelMasaharu Kobayashi (The Univ. of Tokyo)
14:30-14:45Breakout session (QA session)
14:45-14:50IMFEDK/IRPS Call for PapersMutsumi Kimura (Ryukoku Univ.), Kazutoshi Kobayashi (Kyoto Institute of Technology)
Session 3 (Chair: Mutsumi Kimura (Ryukoku Univ.))
14:50-15:05Analog In-Memory Computing in FeFET-Based 1T1R Array for Edge AI ApplicationsDaisuke Saito (Sony Semiconductor Solutions)
15:05-15:20Energy-Efficient Reliable HZO FeFET Computation-in-Memory with Local Multiply & Global Accumulate Array for Source-Follower & Charge-Sharing Voltage SensingChihiro Matsui (The Univ. of Tokyo)
15:20-15:35Chiplet-Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHETakafumi Fukushima (Tohoku Univ.)
15:35-15:503-Dimensional Integration of Epitaxial Magnetic Tunnel Junctions with New Materials for Future MRAMShinji Yuasa (AIST)
15:50-16:053D Stacked CIS Compatible 40nm Embedded STT-MRAM for Buffer MemoryMikio Oka (Sony Semiconductor Solutions)
16:05-16:20Impact of Asymmetric Strain on Performance of Extremely-Thin Body (100) GOI and (110) SGOI pMOSFETsChia Tsong Chen (The Univ. of Tokyo)
16:20-16:25ClosingHirobumi Watanabe (Ricoh)
16:25-16:40Breakout session (QA session)
申し込みフォーム にて申し込みいただきますようお願いいたします。
2021年7月28日(水) 17:00

Last modified: July 29, 2021