IEEE SSCS Kansai Chapterでは，下記の日程で技術セミナーを開催致しました．
今回は，Symposium on VLSI Circuits 2018報告会です．
2018年6月のSymposium on VLSI Circuits（ホノルル，米国）で発表された注目論文を，10名の方
からご講演いただきました．
日時 |
2018年7月10日（火）10:00より16:20 | |
会場 |
神戸大学六甲キャンパス; 百年記念館ホール． Access Map | |
主催 |
IEEE Solid-State Circuits Society Kansai Chapter | |
共催 |
IEEE Solid-State Circuits Society Japan Chapter, 神戸大学大学院科学技術イノベーション研究科 | |
講演 |
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10:00-10:05 |
Opening |
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10:05-10:20 |
Symposium on VLSI Circuits 2018 レビュー講演 Prof. Ken Takeuchi, Chuo University. Symposium on VLSI Circuits 2018 TPC Chair |
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10:20-10:45 |
Lecture 1 "A Two-Tap NIR Lock-In Pixel CMOS Image Sensor with Background Light Cancelling Capability for Non-Contact Heart Rate Detection" C. Cao, Y. Shirakawa, L. Tan, M. W. Seo, K. Kagawa, K. Yasutomi, T. Kosugi*, S. Aoyama*, N. Teranishi, N. Tsumura**, S. Kawahito, Shizuoka University, *Brookman Technology, **Chiba University |
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10:45-11:10 |
Lecture 2 "An 113dB‐Link‐Budget Bluetooth‐5 SoC with an 8dBm 22%‐Efficiency TX" T. Wang, Y. Ogasawara, Y. Tuda, T. Ta*, M. Oshiro, J. Ihara, T. Maruyama, T. Hashimoto, A. Sai*, Takashi Tokairin Toshiba Electronic Devices & Storage Corporation, *Toshiba Corporation |
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11:10-11:35 |
Lecture 3 "Fully Integrated OOK‐powered Pad‐less Deep Sub‐wavelength‐sized 5‐GHz RFID With on‐chip Antenna Using Adiabatic Logic in 0.18μm CMOS" Y. Toeda, T. Fujimaki, M. Hamada, T. Kuroda Keio University |
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11:35-12:00 |
Lecture 4 "12‐nm Fin‐FET 3.0G‐search/s 80‐bit x 128‐Entry Dual‐port Ternary CAM" Makoto Yabuuchi, Masao Morimoto, Koji Nii, Shinji Tanaka Renesas Electronics Corporation |
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12:00-13:30 |
Lunch
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13:30-13:55 |
Lecture 5 "A 1.25MS/s Two‐Step Incremental ADC with 100dB DR and 110dB SFDR" T. Katayama, S. Miyashita, K. Sobue, K. Hamashita Asahi Kasei Microdevices |
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13:55-14:20 |
Lecture 6 "A 2.3‐mW, 950‐MHz, 8‐bit Fully‐Time‐Based Subranging ADC Using Highly‐Linear Dynamic VTC" K. Ohhata Kagoshima University |
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14:20-14:45 |
Lecture 7 "A 64μs Start‐Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi‐Stage Amplifier" M. Miyahara, Y. Endo*, K. Okada**, A. Matsuzawa* High Energy Accelerator Research Organization, *Tokyo Institute of Technology |
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14:45-15:00 |
Break | |
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15:00-15:25 |
Lecture 8 "A 12.8 Gb/s Daisy Chain‐Based Downlink I/F Employing Spectrally Compressed Multi‐Band Multiplexing for High‐ Bandwidth and Large‐Capacity Storage Systems" Y. Tsubouchi, D. Miyashita, Y. Satoh, T. Toi, F. Tachibana, M. Morimoto, J. Wadatsumi, J. Deguchi Toshiba Memory Corporation |
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15:25-15:50 |
Lecture 9 "A 181nW 970μg/√Hz Accelerometer Analog Front‐End Employing Feedforward Noise Reduction Technique" I. Akita, T. Okazawa, Y. Kurui*, A. Fujimoto*, T. Asano Toyohashi University of Technology, *Toshiba Corporation |
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15:50-16:15 |
Lecture 10 "A 92.8% Efficiency Adaptive‐On/Off‐Time Control 3‐Level Buck Converter for Wide Conversion Ratio with Shared Charge Pump Intermediate Voltage Regulator" Y. Karasawa, T. Fukuoka, K. Miyaji Shinshu University |
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16:15-16:20 |
Closing |
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参加費 |
無料 | |