IEEE SSCS Kansai Chapter Technical Seminar

IEEE SSCS Kansai Chapterでは，下記の日程で技術セミナーを開催致しました．
今回はInternatioal Solid-State Circuits Conference (ISSCC) 2015報告会でした．
2015年2月のISSCC（サンフランシスコ，米国）で発表された注目論文を，12名の方 からご講演いただきました．

日時	2015年3月10日（火）9:00より17:20
会場	神戸大学・梅田インテリジェントラボラトリ; 講義室． Access Map
主催	IEEE Solid-State Circuits Society Kansai Chapter
共催	IEEE Solid-State Circuits Society Japan Chapter ISSCC Far-East Regional Committee 神戸大学大学院システム情報学研究科
講演
	9:00-9:05	Opening SSCS Kansai Chapter Chair, Dr. Hideto Hidaka
	9:05-9:30	ISSCC 2015 レビュー講演 Dr. Atsuki Inoue, Fujitsu Lab. Ltd.　 ISSCC Far-East Regional Committee Secretary
	9:30-10:00	Lecture 1 (Non-Volatile Memory Solutions分野), 7.1 "A Low-Power 64Gb MLC NAND-Flash Memory in 15nm CMOS Technology" M. Sako1, Y. Watanabe1, T. Nakajima1, J. Sato1, K. Muraoka1, M. Fujiu1, F. Kouno1, M. Nakagawa1, M. Masuda1, K. Kato1, Y. Terada1, Y. Shimizu1, M. Honma1, A. Imamoto1, T. Araya1, H. Konno1, T. Okanaga1, T. Fujimura1, X. Wang1, M. Muramoto1, M. Kamoshida1, M. Kohno1, Y. Suzuki1, T. Hashiguchi1, T. Kobayashi1, M. Yamaoka1, R. Yamashita2 1Toshiba Semiconductor and Storage Products, Yokohama, Japan 2Sandisk, Yokohama, Japan
	10:00-10:30	Lecture 2 (Non-Volatile Memory Solutions分野), 7.3 "A 28nm Embedded SG-MONOS Flash Macro for Automotive Achieving 200MHz Read Operation and 2.0MB/s Write Throughput at Tj of 170°C" Y. Taito 1, M. Nakano 1, H. Okimoto 1, D. Okada 2, T. Ito 1, T. Kono 1, K. Noguchi 1, H. Hidaka 1, T. Yamauchi 1 1 Renesas Electronics, Itami, Japan 2 Renesas Electronics, Hitachinaka, Japan
	10:30-11:00	Lecture 3 (SoCs for Mobile Vision, Sensing and Communications分野), 18.2 "A 1.9TOPS and 564GOPS/W Heterogeneous Multicore SoC with Color-Based Object Classification Accelerator for Image-Recognition Applications" J. Tanabe, S. Toru, Y. Yamada, T. Watanabe, M. Okumura, M. Nishiyama, T. Nomura, K. Oma, N. Sato, M. Banno, H. Hayashi, T. Miyamori Toshiba, Kawasaki, Japan
	11:00-11:30	Lecture 4 (Image Sensors and Displays分野), 6.2 "133Mpixel 60fps CMOS Image Sensor with 32-Column Shared High-Speed Column-Parallel SAR ADCs" R. Funatsu 1, S. Huang 2, T. Yamashita 1, K. Stevulak 2, J. Rysinski 2, D. Estrada 2, S. Yan 2, T. Soeno 1, T. Nakamura 1, T. Hayashida 1, H. Shimamoto 1, B. Mansoorian 2 1 NHK Science & Technology Research Laboratories, Tokyo, Japan 2 Forza Silicon, Pasadena, CA
	11:30-13:00	Lunch
	13:00-13:30	Lecture 5 (Advanced Wireline Techniques and PLLs分野), 10.1 "A 6Gb/s 6pJ/b 5mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission-Line Coupler and EMC-Qualified Pulse Transceiver" A. Kosuge, S. Ishizuka, J. Kadomoto, T. Kuroda Keio University, Yokohama, Japan
	13:30-14:00	Lecture 6 (Secure, Efficient Circuits for IoT分野), 24.3 "20k-spin Ising Chip for Combinational Optimization Problem with CMOS Annealing" M. Yamaoka, C. Yoshimura, M. Hayashi, T. Okuyama, H. Aoki, H. Mizuno Hitachi, Tokyo, Japan
	14:00-14:30	Lecture 7 (Emerging Technologies Enabling Next-Generation Systems分野), 16.4 "Energy-Autonomous Fever Alarm Armband Integrating Fully Flexible Solar Cells, Piezoelectric Speaker, Temperature Detector, and 12V Organic Complementary FET Circuits" H. Fuketa 1,2, M. Hamamatsu 1,2, T. Yokota 1,2, W. Yukita 1,2, T. Someya 1,2, T. Sekitani 2,3, M. Takamiya 1,2, T. Someya 1,2, T. Sakurai 1,2 1 University of Tokyo, Tokyo, Japan 2 JST/ERATO, Tokyo, Japan 3 Osaka University, Osaka, Japan
	14:30-15:00	Lecture 8 (High-Speed Optical Links分野), 22.2 "A 25Gb/s Hybrid Integrated Silicon Photonic Transceiver in 28nm CMOS and SOI" Y. Chen 1, M. Kibune 1, A. Toda* 2, A. Hayakawa 1,3,4, T. Akiyama 1,3,4, S. Sekiguchi 1,3,4, H. Ebe 1,3,4, N. Imaizumi 1, T. Akahoshi 1, S. Akiyama 3, S. Tanaka 3, T. Simoyama 3, K. Morito 1,3,4, T. Yamamoto 2, T. Mori 1, Y. Koyanagi 1, H. Tamura 1 1 Fujitsu Laboratories, Kawasaki, Japan 2 Fujitsu Laboratories of America, Sunnyvale, CA 3 Photonics Electronics Technology Research Association, Tsukuba, Japan 4 Fujitsu Limited, Kawasaki, Japan
	15:00-15:15	Break
	15:15-15:45	Lecture 9 (High-Speed Optical Links分野), 22.7 "4×25.78Gb/s Retimer ICs for Optical Links in 0.13μm SiGe BiCMOS" T. Shibasaki, Y. Tsunoda, H. Oku, S. Ide, T. Mori, Y. Koyanagi, K. Tanaka, T. Ishihara, H. Tamura Fujitsu Laboratories, Kawasaki, Japan
	15:45-16:15	Lecture 10 (Ultra-High-Speed Wireline Transceivers and Energy-Efficient Links分野), 3.2 "Multi-Standard 185fsrms 0.3-to-28Gb/s 40dB Backplane Signal Conditioner with Adaptive Pattern-Match 36-Tap DFE and Data-Rate-Adjustment PLL in 28nm CMOS" T. Kawamoto 1, T. Norimatsu 1, K. Kogo 1, F. Yuki 1, N. Nakajima 2, M. Tsuge 2, T. Usugi 2, T. Hokari 2, H. Koba 2, T. Komori 2, J. Nasu 2, T. Kawamata 2, Y. Ito 2, S. Umai 2, J. Kumazawa 2, H. Kurahashi 2, T. Muto 2, T. Yamashita 2, M. Hasegawa 2, K. Higeta 2 1 Hitachi, Tokyo, Japan 2 Hitachi, Kanagawa, Japan
	16:15-16:45	Lecture 11 (Energy-Efficient RF Systems分野), 13.8 "A 5.8GHz RF-Powered Transceiver with a 113μW 32-QAM Transmitter Employing the IF-based Quadrature Backscattering Technique" A. Shirane, H. Tan, Y. Fang, T. Ibe, H. Ito, N. Ishihara, K. Masu Tokyo Institute of Technology, Tokyo, Japan
	16:45-17:15	Lecture 12 (Digital PLLs and SoC Building Blocks分野), 14.1 "A 0.048mm2 3mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique" W. Deng, D. Yang, A. T. Narayanan, K. Nakata, T. Siriburanon, K. Okada, A. Matsuzawa Tokyo Institute of Technology, Tokyo, Japan
	17:15-17:20	Closing
	参加者	56名（IEEE Member：35名、Non-Member：21名）
	講演者と役員