IEEE SSCS Kansai Chapter Technical Seminar

IEEE SSCS Kansai Chapterでは,下記の日程で技術セミナーを開催致しました.
今回はIEEE Symposium on VLSI Circuits報告会でした.

2010年6月30日(水曜日) 13:15より17:00
神戸国際会館 9F 大会場 (開場13:00)
“Symposium on VLSI Circuits 2010 Overview,” Makoto Nagata, Kobe University.
#5.2 “A 5-20GHz Tunable LC-VCO using Variable Bridge Inductor,” A. Tanabe, K. Hijioka, H. Nagase, Y.Hayashi, NEC Electronics Corp, Japan
A wide frequency range tunable LC-VCO is developed using a novel multi-stage variable inductor which has a bridge architecture and a miniature 3D solenoid structure. Because of this inductor, over 15GHz continuous tuning range up to 20GHz is achieved with 10.6mW total power consumption. Phase noise at 1MHz offset is -103dBc/Hz (@10GHz) and -87dBc/Hz (@20GHz). This miniature variable inductor also realizes chip area smaller than 1/10 of reported wide range LC-VCOs.
#7.4 “FDM-based Wireless Source Synchronous 15-Mbps TRx with PLL-less Receiver and 1-mm Onchip Integrated Antenna for 1.25-cm Touch-and-Proceed Communication,” H. Ishizaki, T. Araki*, S.Takahashi, J. Ryu*, S. Uchida**, N. Yoshida, M. Takamiya*, M. Mizuno, NEC Corporation, Japan, *The University of Tokyo, Japan, **NEC Electronics Corporatio, Japan
A 15-Mbps, single-channel wireless source synchronous (SWSS) transceiver with a 1-mm on-chip integrated loop antenna has been developed in 90-nm CMOS for 1.25-cm ‘touch-and-proceed communication’ between electronic devices. A newly developed FDM-based SWSS architecture makes simultaneous CLOCK and DATA transmission possible with only a single antenna as well as the elimination of PLL and clock recovery blocks in Rx. We have successfully demonstrated a 1.0-cm robust alignment of antenna position for 1.0-cm communication distance with a 1-mm on-chip antenna at BER<10-5.
#19.2 “Simultaneous 6Gb/s Data and 10mW Power Transmission using Nested Clover Coils for Non-Contact Memory Card,” Y. Yuan, A. Radecki, N. Miura, I. Aikawa, Y. Take, H. Ishikuro, T. Kuroda, Keio University.
This paper presents a non-contact memory card and a host employing simultaneous data and power transmission through inductive coupling. Nested clover-shaped data coils are proposed for reducing interference from a power link. The host wirelessly tracks current consumption of the card and adjusts transmit power to improve power transfer efficiency. The prototype is implemented in 65nm CMOS. It achieves 6Gb/s data rate and almost 10% power transfer efficiency over a 100-2k ohm range of the load.
#17.3 “A 6-phase Harmonic Rejection Down-Converter with Digital Assist,” T. Yamaji, J. Matsuno, H. Aoyama, M. Furuta, T. Takida, I. Akita, A. Kuroda, T. Itakura, N. Itoh, Toshiba Corp.
A down-converter insensitive to 2nd and 3rd harmonics and a digital assisting circuit that cancels residual sensitivity due to device mismatches are proposed. Measured 2nd and 3rd harmonic rejection ratios of over 60 dB are achieved. This performance allows a simple RF filter, and it is effective to reduce the die size.
#12.2 “On-Chip Waveform Capture and Diagnosis of Power Delivery in SoC Integration,” T. Hashida, M. Nagata, Kobe University.
On-chip waveform capture exhibits the resolution of 10 ps and 200 uV with 1024 steps, and SFDR of 63.2dB in 700- MHz signal bandwidth of interest. On-chip signal probing as well as digital waveform processing are merged in systems-on- chip (SoC) integration. An exciter is combined for on-chip derivation of LCR parasitics from oscillatory waveforms of a power delivery network that are effectively seen by SoC circuits.
#12.1 “Resonant Supply Noise Canceller utilizing Parasitic Capacitance of Sleep Blocks,” J. Kim, T. Nakura, H. Takata*, K. Ishibashi*, M. Ikeda, K. Asada, University of Tokyo, Japan, *Renesas Technology Corp.
This paper proposes a resonant supply noise canceller utilizing parasitic capacitance of sleep blocks. It has small area penalty because we use sleep blocks for noise cancelling. Measurement results show that the test chip fabricated in 0.18um CMOS process achieved 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. These results make fast switching of power mode possible for DVS and power gating.
#12.3 “65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop Capable of Protecting Soft Errors on the C-element,” J. Furuta, C. Hamanaka*, K. Kobayashi*, H. Onodera, Kyoto University, *Kyoto Institute of Technology.
We propose a Bistable Cross-coupled Dual Modular Redundancy (BCDMR) Flip-Flop to enhance soft-error immunity. It is based on a BISER FF but its cross-coupled structure enhances soft-error immunity without any area/delay overhead. We fabricated a 65nm LSI including 60,480bit shift registers with the BCDMR and BISER structures. Experimental results using alpha-particles reveals that the soft-error immunity of the BCDMR is enhanced by 150x at 160MHz clock frequency compared with the BISER FFs.
#4.2 “Small-defect detection in sub-100nm SRAM cells using WL-pulse timing-margin measurement scheme,” Y. Morita, K. Nose, K. Noguchi, S. Takami*, K. Goto*, S. Aimoto*, A. Kimura*, M. Mizuno, NEC Corporation, *NEC Electronics Corp.
The detection of small defects in an SRAM cell with our WL-pulse timing-margin measurement scheme has been demonstrated on a 90nm 2Mb SRAM. WL-width control with a high resolution of 24.1ps and a wide range improves the sensitivity of detection for delay and SNM variations with only a 0.6% area overhead, and statistical analysis makes possible the detection of small-delay defects that, in conventional testing, would be buried due to delay variations in peripheral circuitry.
#10.1 “A 28-nm Dual-Port SRAM Macro with Active Bitline Equalizing Circuitry Against Write Disturb Issue,” Y. Ishii, H. Fujiwara, K. Nii, H. Chigasaki, O. Kuromiya,T. Saiki, A.Miyanishi, Y. Kihara, Renesas Technology Corp.
We propose circuit techniques for an 8T dual-port SRAM to improve its minimum operating voltage. Active bitline equalizing technique improves the write margin whenever a write-disturb occurs. It is applicable for both synchronous and asynchronous clock frequencies between ports. We designed and fabricated a 256kb SRAM macro using 28-nm low-power technology and achieved low-voltage operation at 0.66V and 1.4ns write access time at 25°C, which are 120mV lower and 40% faster than the conventional performance.
57名 (内学生33名)

Last modified: Jul. 1, 2010