題 目： Power Integrity of IC and 3D Package (ICと3次元パッケージのパワーインテグリティ)
講 師： Professor Joungho Kim, Korea Advanced Institute of Science and Technology (KAIST), Korea

▼講演内容概要

Power supply noise by digital switching is becoming the major source of electromagnetic noise generation and coupling in semiconductor systems. It could be even more serious in 3D SiP and IC based on vertical TSV type interconnections for high-density and multi-function mobile multimedia, computing, and communication system platforms. In this talk, new modeling, design, and analysis approaches will be introduced with the consideration of the power integrity. The unique methods are based on simultaneous and hierarchical chip-package co-design and modeling in order to offer cost effective design solutions. In particular, we will shown novel design methods and test results including thin film capacitor and EBG structures to minimize the power supply noise generation and coupling.

1. Introduction
2. Power integrity of IC
3. Power integrity of package
4. Modeling and analysis of hierarchical PDN
5. Hierarchical decoupling and high dielectric thin film design
6. Noise generation and coupling by via and PDN’s
7. EBG structure and suppression of SSN
8. PDN effects on RF and analog circuits.
9. PDN design issues in 3D IC based on TSV
10. Conclusions.

▼講師略歴

Dr. Joungho Kim received B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and Ph.D degree in electrical engineering from the University of Michigan, Ann Arbor, in 1993. In 1994, he joined Memory Division of Samsung Electronics, where he was engaged in Gbit-scale DRAM design.

In 1996, he moved to KAIST (Korea Advanced Institute of Science and Technology). He is currently a Professor at Electrical Engineering and Computer Science Department, and the group director of Convergence Device and System Group. Since joining KAIST, his research centers on EMC modeling, design, and measurement methodologies of 3D IC, System-in-Package(SiP), and multi-layer PCB. Especially, his major research topic is focused on chip-package co-design and simulation for signal integrity, power integrity, ground integrity, timing integrity, and radiated emission of 3D IC and SiP. He has successfully demonstrated low noise and high performance designs of numerous SiP’s for wireless communication applications such as ZigBee, T-DMB, NFC, and UWB. He was on a sabbatical leave during an academic year from 2001 to 2002 at Silicon Image Inc., Sunnyvale CA. He was responsible for low noise package designs for SATA, FC, HDMI, and Panel Link SerDes devices.

He has authored and co-authored over 280 technical papers published at refereed journals and conference proceedings in modeling, design, and measurement of 3D IC, SiP, and PCB. Also, he has given more than 130 invited talks and tutorials at the academia and the related industries. He received Outstanding Academic Achievement Faculty Award of KAIST in 2006, and Best Faculty Research Award of KAIST in 2008. Dr. Joungho Kim was the symposium chair of IEEE EDAPS 2008 Symposium. He is appointed as an IEEE EMC society distinguished lecturer in a period from 2009-2011. Currently, he is an associated editor of the IEEE Transactions of Electromagnetic Compatibility, and is serving as a guest editor of the special issue in the IEEE Transactions of Electromagnetic Compatibility for PCB level signal integrity, power integrity, and EMI/EMC.

▼開催要領

会　期： 2009年（平成21年）7月17日（金）16:00〜18:00
会　場： キャンパスプラザ京都（京都市下京区西洞院通塩小路下る）
　　　　　4階 第4講義室
会　費： 無料

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